A high resolution DDFS design on VHDL using Bipartite Table Method
DOI:
https://doi.org/10.21533/pen.v5.i3.2059Abstract
In this study, a Look Up Table (LUT) based Direct Digital Frequency Synthesizer (DDFS) is designed on VHDL. Bipartite Table Method, an advance memory compression method, is used together with quadratic compression method. 23 mHz frequency resolution is achieved with 100MHz clock input. The required memory is obtained 585 times smaller than traditional DDFSs. A MATLAB code is revealed to select the best design which provides the smallest required memory for 100 dB Spurious Free Dynamic Range (SFDR) level. The contents of the LUTs are also evaluated by using MATLAB software. The design is simulated for multiple frequencies between 23mHz-30MHz with VIVADO 2016.3 software. The simulation results perfectly match with calculations.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
