Design and implementation 4x4 Network on Chip (NoC) using FPGA
DOI:
https://doi.org/10.21533/pen.v10.i3.668Abstract
Network on Chip is one of the most crucial in the development of the networks and routers in new days due to the improvement that make through way of sending huge packets of data and technology and protocol that used for sending the packets between IP cores. Also, the NoC is removed the old ways of technique and protocols of sending packets through routers. The NoC is the most enhanced and efficient in working in parallel ways. Hence, Field Program Gate Array (FPGA) is used in the designing of router that its architecture depending on the NoC. The research proposed in this paper proposed 4x4 nodes router with mesh network that support two-dimensional architecture. A real time test is used for experimental through FPGA and the test verified efficient packets transporting via two array buffers that integrated in the proposed router architecture.
Downloads
Published
Issue
Section
License
This work is licensed under a Creative Commons Attribution 4.0 International License.
Authors retain copyright and grant the journal right of first publication with the work simultaneously licensed under a Creative Commons Attribution License that allows others to share the work with an acknowledgement of the work's authorship and initial publication in this journal.
Authors are able to enter into separate, additional contractual arrangements for the non-exclusive distribution of the journal's published version of the work (e.g., post it to an institutional repository or publish it in a book), with an acknowledgement of its initial publication in this journal.
