A high resolution DDFS design on VHDL using bipartite table method

Yunus Emre Acar, Ercan Yaldiz


In this study, a Look Up Table (LUT) based Direct Digital Frequency Synthesizer (DDFS) is designed on VHDL. Bipartite Table Method, an advance memory compression method, is used together with quadratic compression method. 23 mHz frequency resolution is achieved with 100MHz clock input. The required memory is obtained 585 times smaller than traditional DDFSs. A MATLAB code is revealed to select the best design which provides the smallest required memory for 100 dB Spurious Free Dynamic Range (SFDR) level. The contents of the LUTs are also evaluated by using MATLAB software. The design is simulated for multiple frequencies between 23mHz-30MHz with VIVADO 2016.3 software. The simulation results perfectly match with calculations.


bipartite table method; quadratic compression; DDFS; DDS; VHDL

Full Text:



C.Nie, X.Wang, H.Zhao, “W-band Transceiver Design of FMCW Radar with High Resolution”, 5th IEEE International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 2013, pp. 691-693.

A. Al Safi, B. Bazuin, “FPGA Based Implementation of BPSK and QPSK Modulators Using Address Reverse Accumulators”, IEEE 7th Annual Ubiquitous Computing, Electronics & Mobile Communication Conference (UEMCON), 2016, pp. 1-6.

D. Sarriá, O. Pallarés, J. del-Río Fernández, A. Mànuel-Làzaro, “Low Cost OFDM Based Transmitter for Underwater Acoustic Communication”, MTS/IEEE OCEANS, Bergen, 2013, pp. 1-4.

S. Yunxia, C. Bingyan, Z. Juan, T. Yingying, G. Yuan and S. Minglei, “Design of Time-Delay Detection Equipment for Signal Circuit”, 12th International Conference on Electronic Measurement & Instruments, 2015, pp. 824-830.

C. Lv, D. Fan, B. Shi, W. Wang and Z. Liu, “A Distortion Tester of Geophone Based on FPGA”, IEEE International Conference on Automation and Logistics (ICAL), 2009, pp. 1289-1092.

X. Cheng, H. Zhao, Y. Dai and X. Liu, “Image Acquisition Design of the AOTF Imaging Spectrometer Based on SOPC”, International SoC Design Conference (ISOCC), 2011, pp. 266-269.

K. Peng , X. Liu and P. Huang, “Study on The Wireless Energy Supply System in The Implantable Cardiac Pacemaker”, 6th International Conference on Intelligent Systems Design and Engineering Applications (ISDEA), 2015, pp. 778-781.

R. Storch and T. Musch, “Synthesis Concepts of Signals With High Spectral Purity for the Use in Impulse Radar Systems”, IEEE Transactions on Instrumentation and Measurement, vol. 64, pp. 2574-2582, Sept. 2015.

S. Thuries, E. Tournier and J. Graffeuil, “A 3-bits DDS Oriented Low Power Consumption 15 GHz Phase Accumulator in a 0.25 μm BiCMOS SiGe:C Technology”, 13th IEEE International Conference on Electronics, Circuits and Systems (ICECS ) , 2006, pp. 991-994.

H. Jafari, A. Ayatollahi, and S. Mirzakuchaki, ” A Low Power, High SFDR, ROM-less Direct Digital Frequency Synthesizer”, IEEE Conference on Electron Devices and Solid-State Circuits, 2005, 829-832.

S. Yanbin, G. Jian and C. Ning, “High Precision Digital Frequency Signal Source Based on FPGA”, International Conference on Solid State Devices and Materials Science, 2012, pp. 1342-1347.

F. Dinechin and A. Tisserand,“Multipartite Table Methods”, IEEE Transactions On Computers, vol.54, pp. 319-330, Mar. 2005.

A. G. M. Strollo, D. De Caro and N. Petra, “A 630 MHz, 76 mW Direct Digital Frequency Synthesizer Using Enhanced ROM Compression Technique”, IEEE Journal of Solid-State Circuits, vol.42, pp. 350–360, Feb. 2007.

D. De Caro, N. Petra, and A. G. M. Strollo, “Reducing Lookup-Table Size in Direct Digital Frequency Synthesizers Using Optimized Multipartite Table Method”, IEEE Transactions On Circuits And Systems, vol.55, pp. 2116-2127, Aug. 2008.

T. Menakadevi and M. Madheswaran, “Direct Digital Synthesizer using Pipelined CORDIC Algorithm for Software Defined Radio”, International Journal of Science and Technology, vol. 2, pp.372-378, June 2012.

Y.H. Chen and Y. A. Chau, “A Direct Digital Frequency Synthesizer Based on a New Form of Polynomial Approximations”, IEEE Transactions on Consumer Electronics, vol.56, pp. 436-440, May. 2010.

Y. Song and B. Kim,“A 14-b Direct Digital Frequency Synthesizer With Sigma-Delta Noise Shaping,”, IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 847–851, May 2004.

DOI: http://dx.doi.org/10.21533/pen.v5i3.116


  • There are currently no refbacks.

Copyright (c) 2017 Periodicals of Engineering and Natural Sciences (PEN)

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License.

ISSN: 2303-4521

Digital Object Identifier DOI: 10.21533/pen

Creative Commons License
This work is licensed under a Creative Commons Attribution 4.0 International License