MESI protocol for multicore processors based on FPGA

Abstract

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So, if one core requests a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores. This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using VHDL coding and implemented using ISE Xilinx software, one protocol was used in this design, the MESI (Modify, Exclusive, Shared and Invalid) protocol. Test results were taken by using test bench, and showed all the states of the protocols are working correctly.