A high resolution DDFS design on VHDL using Bipartite Table Method

In this study, a Look Up Table (LUT) based Direct Digital Frequency Synthesizer (DDFS) is designed on VHDL. Bipartite Table Method, an advance memory compression method, is used together with quadratic compression method. 23 mHz frequency resolution is achieved with 100MHz clock input. The required memory is obtained 585 times smaller than traditional DDFSs. A MATLAB code is revealed to select the best design which provides the smallest required memory for 100 dB Spurious Free Dynamic Range (SFDR) level. The contents of the LUTs are also evaluated by using MATLAB software. The design is simulated for multiple frequencies between 23mHz-30MHz with VIVADO 2016.3 software. The simulation results perfectly match with calculations.


Introduction
Frequency synthesizers are the systems that generate signals with new frequencies from one or more reference signal.In the history of frequency synthesizers, several approaches are proposed to synthesize new frequencies and these approaches are divided in three major groups.These are Direct Analog, Direct Digital and Indirect Frequency Synthesizers.Direct Digital Synthesis is the one which provides fast switching speed, very high frequency resolution, low phase noise, ease to control output frequency precisely and utilized in several areas such as communication [1]- [3] test and measurement systems [4], [5], image processing [6] and medical applications [7].A typical Direct Digital Frequency Synthesizer (DDFS) uses ROMs as Look Up Tables (LUTs) to convert the phase values to amplitude values.The ROMs contains the digital samples of the desired signal form.A counter is used as a phase accumulator.The phase accumulator controls the frequency of the output signal with a digital Frequency Tuning Word (FTW).The word changes the step size of the address counter of the ROM.Thus, the desired frequency is adjusted digitally.The output frequency is evaluated by the following equation where f is the reference clock signal and N is the number of phase values on the counter.
A Digital to Analog Converter (DAC) is used to get the analog signal.Principle stages of a DDFS are given in Fig. 1.

Figure 1. Principal stages of a traditional LUT based DDFS
In DDFS designs, many improvements are revealed to achieve better spectral performance [8], lower power dissipation [9], [10], higher frequency resolution [11] and smaller required area [12]- [14].This paper presents a high resolution, LUT based DDFS design on VHDL.Bipartite Table Method (BTM) which is offered by Dinechin and Tisserand in 2005 is used to lessen the LUT size while keeping the Spurious Free Dynamic Range (SFDR) above 100 dB.

LUT Based DDFSs
In DDFS, the phase to amplitude conversion is done in several ways.LUT based [12]- [14],iterative approaches [15] and LUT free approaches [16] are the most common ones of these ways.LUTs are the tables that store the sampled data of a signal form.The size of the LUT determines the resolution and the spectral performance of the signal to be generated.Table 1 shows the content of a 32x8 bits LUT for a sine.As shown from the Table 1, the LUT stores 32 digital data represented with 8 bits signed numbers.When a sine is generated from this small LUT, the approximate SFDR value of the generated signal is evaluated as 53.62 dB with the sfdr (x) command in MATLAB.Although the spectral performance seems good, the phase and amplitude resolutions are both unsatisfactory.The generated sine is shown in Fig. 2. The increase in resolution or spectral performance requires an increase in the LUT size.De Caro and his friends claim that their design requires only 208 bits to provide higher SFDR level with 11 bits phase and 9 bit amplitude resolution.To obtain this much phase and amplitude resolution, a 18,432 bits-LUT is required in a traditional DDFS structure.There are several LUT based studies providing 100 dBc and higher SFDR levels with very high phase and amplitude resolution [14], [17].The common idea behind these studies is to compress the ROM size as much as possible while keeping the SFDR level and the resolutions good enough.In this design, BTM is used to compress the ROM while keeping the SFDR above the predetermined levels.

Bipartite Table Method (BTM)
In this part of the paper BTM which is the one of the LUT based approaches is introduced.The method uses piecewise linear approach.In this method two different LUT is used.Firstly, initial values are evaluated and stored in the first LUT.This table is called table of initial values (TIV).Fig. 3 shows the initial values for the one fourth of a sine period for 32 initial values with the 8 bit amplitude resolution (R).The TIV size is calculated as Secondly, some offset values are evaluated and stored in the second LUT.The table is called as table of offsets (TO).The TO values are calculated by using piecewise linear approach with the following equations.
Figure 3.The initial values for the one fourth of sine period In BTM, the idea is to use same slope value for some adjacent points.Thus, the x axis is divided into equal intervals where b < .The same slope value is used for the − adjacent points in each interval.The TO size is calculated as where is the number of offset value for each initial value.Fig. 4 gives the approximated  where 0≤x≤π/2with BTM.The function is evaluated as Figure 4. Approximated sine using BTM with R=8, a=4, b=2, c=2 As previously mentioned, LUT stage of a DDFS converts the phase value from the phase accumulator to amplitude values.To do this, it uses the P bit phase information as the address counter of both the TIV and the TO.First a bits of the word is used for the TIV, and the rest c bits and the most significant b bits of the word is also used for the TO.The decomposition of phase the word is given in Fig. 5.
Figure 5. Phase word decomposition

𝑃 𝑖 𝑃ℎ
TIV TO   Figure 6.Block scheme of the counter

Best Decomposition of the Phase Word
Thegoal is todesign a DDFS with 18 bitsphaseand 16 bitsamplituderesolutionand a SFDR levelover 100 dB.
An algorithm is createdtofindoutbestdecomposition of thephasewordtoobtainthetarget SFDR withthe minimum size of therequiredmemory.TheMatlabcode of thealgorithm is given in Fig. 7. Byusingthealgorithm, theparameters a, b and c arefound as 10, 3 and 8, respectively.
Figure 7.Matlab code of the best decomposition algorithm

Figure 2 .
Figure 2. The sine generated from the 32x8 bits LUT

Figure 8 .Figure 9 .
Figure 8. Block scheme of the phase to amplitude conversion stage